In existing processing systems, especially in mobile environments, power consumption requirements directly affect battery life. Furthermore, power consumption can drive processing capabilities and further drive processing speeds. In a typical processing environment, therefore, power consumption is an important factor to monitor and attempt to minimize. Minimized power consumption is sought not only during normal operations through efficient processing but also through the disablement of processing elements during idle times.
One common approach to power saving and power consumption reduction is the disabling of processing elements during idle times. In more common terms, this may be similar to a computer or other processing device entering a “sleep mode” or a “standby mode.” To disable a particular processing element, such as a central processing unit or a graphics processor, clocks may be gated off completely. This typically entails gating off a clock frequency, such as setting the clock frequency to zero. In a typical graphics processing environment, a graphics engine may have multiple clocks for the 2D and 3D engines.
The current approach to power consumption is an all or nothing scenario for powering down. In this technique, a processor or a particular engine within the processor is either ON or OFF. Therefore, when a processing system enters a stall mode, the current approach does not allow for reduction in power consumption. Especially in an integrated chipset environment, processing system stalls may arise for reasons outside of the graphics engines, such as delays in a memory interface. During this scenario, this graphics processor is not in an idle or sleep mode, but rather is inactive awaiting further operations. Therefore, the graphics processor is unable to power down, but rather must maintain full power during the system stall time interval.
For example, if a graphics processing engine is coupled to one or more memory modules through a memory controller, the performance of the graphics processing engine may be dependent on the efficiency of data transfer through the memory controller. In an integrated chipset environment, a northbridge may further couple the memory controller to a central processing unit. The memory controller may further be coupled to an output display. Therefore, there exists the potential for processing delays at various processing levels, wherein the current power saving approach is unable to effectively remedy power consumption in view thereof.
In other words, the current power consumption reduction techniques include reducing power when the system is in an idle or sleep mode, but fails to account for power reduction during a stall mode. Therefore, there exists a need for applicable reduction of power consumption requirements for a graphics processing device during non-idle times.